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LD7575 6/16/2008 1 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 green-mode pwm controller with high-voltage start-up circuit rev: 04b general description the LD7575 is a current-mode pwm controller with excellent power-saving operati on. it features a high- voltage current source to di rectly supply the startup current from bulk capacitor and further to provide a lossless startup circuit. the integrated functions such as the leading-edge blanking of t he current sensing, internal slope compensation, and the small package provide the users a high efficiency, minimum external component counts, and low cost solution for ac/dc power applications. furthermore, the embedded over voltage protection, over load protection and the special green-mode control provide the solution for users to design a high performance power circuit easily. the LD7575 is offered in both sop-8 and dip-8 package. features z high-voltage (500v) startup circuit z current mode control z non-audible-noise green mode control z uvlo (under voltage lockout) z leb (leading-edge blanking) on cs pin z programmable switching frequency z internal slope compensation z ovp (over voltage protection) on vcc z olp (over load protection) z 500ma driving capability applications z switching ac/dc adapter and battery charger z open frame switching power supply z lcd monitor/tv power typical application
LD7575 2 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 pin configuration yy: year code ww: week code pp: production code sop-8 & dip-8 (top view) 1 8 2 3 4 7 6 5 top mark yywwpp rt comp cs gnd hv nc vcc out ordering information part number package top mark shipping LD7575 gs sop-8 green package LD7575gs 2500 /tape & reel LD7575 ps sop-8 pb free LD7575ps 2500 /tape & reel LD7575 pn dip-8 pb free LD7575pn 3600 /tube /carton the LD7575 is rohs compliant/ green package. pin descriptions pin name function 1 rt this pin is to program the switching frequency. by connecting a resistor to ground to set the switching frequency. 2 comp voltage feedback pin (same as the co mp pin in uc384x), by connecting a photo-coupler to close the control loop and achieve the regulation. 3 cs current sense pin, connec t to sense the mosfet current 4 gnd ground 5 out gate drive output to drive the external mosfet 6 vcc supply voltage pin 7 nc unconnected pin 8 hv connect this pin to positive terminal of bulk capacitor to provide the startup current for the controller. when vcc voltage trips t he uvlo(on), this hv loop will be off to save the power loss on the startup circuit.
LD7575 3 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 block diagram osc comp cs out internal bias & vref vcc gnd pwm comparator rt 16.0v/ 10.0v green-mode control leading edge blanking 2r r r sq vref ok pg + + slope compensation 27.5v hv 0.85v 30ms delay 5.0v ocp comparator olp comparator ovp uvlo comparator driver stage ovp comparator r sq vcc ok olp pg 8v por /2 counter clear por vbias 32v 1ma r sq pg
LD7575 4 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 absolute maximum ratings supply voltage vcc 30v high-voltage pin, hv -0.3v~500v comp, rt, cs -0.3 ~7v maximum junction temperature 150 c operating ambient temperature -40 c to 85 c operating junction temperature -40 c to 125 c storage temperature range -65 c to 150 c package thermal resistance (sop-8) 160 c/w package thermal resistance (dip-8) 100 c/w power dissipation (sop-8, at ambient temperature = 85 c) 400mw power dissipation (dip-8, at ambient temperature = 85 c) 650mw lead temperature (soldering, 10sec) 260 c esd voltage protection, human body model (except hv pin) 3kv esd voltage protection, machine model 200v gate output current 500ma caution: stresses beyond the ratings specified in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above t hose indicated in the operational sections of this s pecification is not implied. recommended operating conditions item min. max. unit supply voltage vcc 11 25 v vcc capacitor 10 47 f switching frequency 50 130 khz
LD7575 5 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 electrical characteristics (t a = +25 o c unless otherwise stated, v cc =15.0v) parameter conditions min typ max units high-voltage supply (hv pin) high-voltage current source v cc< uvlo(on) 0.5 1.0 1.5 ma off-state leakage current vcc> uvlo(off) 35 a supply voltage (vcc pin) startup current 100 a v comp =0v 2.0 3.0 ma v comp =3v 2.5 4.0 ma operating current (with 1nf load on out pin) protection tripped (olp, ovp) 0.5 ma uvlo (off) 9.0 10.0 11.0 v uvlo (on) 15.0 16.0 17.0 v ovp level 25.0 27.5 30.0 v voltage feedback (comp pin) short circuit current v comp =0v 1.5 2.2 ma open loop voltage comp pin open 6.0 v green mode threshold vcomp 2.35 v current sensing (cs pin) maximum input voltage 0.80 0.85 0.90 v leading edge blanking time 350 ns input impedance 1 m delay to output 100 ns oscillator (rt pin) frequency rt=100k 60.0 65.0 70.0 khz green mode frequency fs=65.0khz 20 khz temp. stability (-40 c ~105 c) 3 % voltage stability (vcc=11v-25v) 1 % gate drive output (out pin) output low level vcc=15v, io=20ma 1 v output high level vcc=15v, io=20ma 9 v rising time load capacitance=1000pf 50 160 ns falling time load capacitance=1000pf 30 60 ns olp (over load protection) olp trip level 5.0 v olp delay time (note) fs=65khz 30 ms
LD7575 6 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 note: the olp delay time is proportional to the period of swit ching cycle. so that, the lower rt value will set the higher switching frequency and the shorter olp delay time. typical performance characteristics hv current source (ma) temperature ( c) fig. 1 hv current source vs. temperature (hv=500v, vcc=0v) 0.7 0.9 1.1 1.3 1.5 -40 0 40 80 120 125 v cs (off) (v) temperature ( c) fig. 2 v cs (off) vs. temperature 0.85 0.86 0.87 0.88 0.89 0.90 -40 0 40 80 120 125 uvlo (on) (v) fig. 3 uvlo (on) vs. temperature temperature ( c) 14.0 14.8 15.6 16.4 17.2 18.0 -40 0 40 80 120 125 uvlo (off) (v) temperature ( c) fig. 4 uvlo (off ) vs. temperature 8 9.6 10.4 12 8.8 -40 0 40 80 120 125 11.2 frequency (khz) fig. 5 frequency vs. temperature temperature ( c) -40 60 62 64 66 68 70 0 40 80 120 125 frequency (khz) temperature ( c) fig. 6 green mode frequency vs. temperature 16 18 20 22 24 26 -40 0 40 80 120 125
LD7575 7 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 frequency (khz) vcc (v) fig. 7 frequency vs. vcc 12 14 16 18 20 22 24 60 11 25 62 64 66 68 70 green mode frequency (khz) vcc (v) fig. 8 green mode frequency vs. vcc 12 14 16 18 20 22 24 11 25 19 21 23 25 17 15 max duty (%) temperature ( c) fig. 9 max duty vs. temperature -40 0 40 80 120 125 65 70 75 80 85 60 vcc ovp (v) temperature ( c) fig. 10 vcc ovp vs. temperature 10 15 20 25 30 35 -40 0 40 80 120 125 v comp (v) temperature ( c) fig. 11 v comp open loop voltage vs. temperature -40 0 40 80 120 125 4.5 5.0 5.5 6.0 6.5 7.0 olp (v) temperature ( c) fig. 12 olp-trip level vs. temperature -40 0 40 80 120 125 3.5 4.0 4.5 5.0 5.5 6.0
LD7575 8 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 application information operation overview as long as the green power requirement becomes a trend and the power saving is getting more and more important for the switching power supplies and switching adaptors, the traditional pwm controllers are not able to support such new requirements. furt hermore, the cost and size limitation force the pwm contro llers need to be powerful to integrate more functions to reduce the external part counts. the LD7575 is targeted on such application to provide an easy and cost effective solution; its detail features are described as below: internal high-voltage startup circuit and under voltage lockout (uvlo) r1 out cs vcc gnd LD7575 c1 cbulk d1 rs comp vin hv fig. 13 traditional circuit powers up the pwm controller through a startup resistor to provide the startup current. however, the startup resistor consumes significant power which is more and more critical whenever the power saving requirement is coming tight. theoretically, this startup resistor can be very high resistance value. however, higher resistor value will cause longer startup time. to achieve an optimized topology, as shown in figure 13, LD7575 implements a high-voltage startup circuit for such requirement. during the startup, a high-voltage current source sinks current from the bulk capacitor to provide the startup current as well as charge the vcc capacitor c1. during the startup transient , the vcc is lower than the uvlo threshold thus the current source is on to supply a current with 1ma. meanwhile, the vcc supply current is as low as 100 a thus most of the hv current is utilized to charge the vcc capacitor. by using such configuration, the turn-on delay time will be almost same no matter under low-line or high-line conditions. whenever the vcc voltage is higher than uvlo(on) to power on the LD7575 and further to deliver the gate drive signal, the high-voltage current source is off and the supply current is provided from the auxiliary winding of the transformer. therefore, the power losses on the startup circuit can be eliminated and the power saving can be easily achieved. an uvlo comparator is incl uded to detect the voltage on the vcc pin to ensure the supply voltage enough to power on the LD7575 pwm controller and in addition to drive the power mosfet. as shown in fig. 14, a hysteresis is provided to prevent the shut down from the voltage dip during startup. the turn-on and turn-off threshold level are set at 16v and 10.0v, respectively. vcc uvlo(on) uvlo(off) t t hv current 1ma startup current (<100ua) vcc current ~ 0ma (off) operating current (supply from auxiliary winding)
LD7575 9 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 fig. 14 current sensing, leading-edge blanking and the negative spike on cs pin the typical current mode pwm controller feedbacks both current signal and voltage signal to close the control loop and achieve regulation. the LD7575 detects the primary mosfet current from the cs pi n, which is not only for the peak current mode control but also for the pulse-by-pulse current limit. the maximum voltage threshold of the current sensing pin is set as 0.85v. thus the mosfet peak current can be calculated as: s ) max ( peak r v 85 . 0 i = a 350ns leading-edge blanking (leb) time is included in the input of cs pin to prevent the false-trigger caused by the current spike. in the low po wer application, if the total pulse width of the turn-on spikes is less than 350ns and the negative spike on the cs pi n is not exceed -0.3v, the r-c filter (as shown in figure15) can be eliminated. however, the total pulse widt h of the turn-on spike is related to the output power, circuit design and pcb layout. it is strongly recommended to add the small r-c filter (as shown in figure 16) for higher power application to avoid the cs pin damaged by the negative turn-on spike. output stage and maximum duty-cycle an output stage of a cmos buffer, with typical 500ma driving capability, is incorporated to drive a power mosfet directly. and the maximum duty-cycle of LD7575 is limited to 75% to avoid the transformer saturation. voltage feedback loop the voltage feedback signal is provided from the tl431 in the secondary side through the photo-coupler to the comp pin of LD7575. the input stage of LD7575, like the uc384x, is with 2 diodes voltage offset then feeding into the voltage divider with 1/3 ratio, that is, ) v 2 v ( 3 1 ) v f comp pwm ( comparator ? = + a pull-high resistor is embedded internally thus can be eliminated on the external circuit. cs vcc gnd LD7575 can be removed if the negative spike is not over spec. (-0.3v). out 350ns blanking time fig. 15 fig. 16
LD7575 10 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 oscillator and switching frequency connecting a resistor from rt pin to gnd according to the equation can program the normal switching frequency: ) khz ( 100 rt 0 . 65 f ) k ( sw = the suggested operating frequency range of LD7575 is within 50khz to 130khz. internal slope compensation a fundamental issue of current mode control is the stability problem when its duty-cycle is operated more than 50%. to stabilize the control loop, the slope compensation is needed in the traditional uc384x design by injecting the ramp signal from the rt/ct pin through a coupling capacitor. in LD7575, the internal slope compensation circuit has been implemented to simplify the external circuit design. on/off control the LD7575 can be controlled to turn off by pulling comp pin to lower than 1.2v. t he gate output pin of LD7575 will be disabled immediately under such condition. the off mode can be released when the pull-low signal is removed. dual-oscillator green-mode operation there are many difference topologies has been implemented in different chips for the green-mode or power saving requirements such as ?burst-mode control?, ?skipping-cycle mode?, ?variable off-time control ??etc. the basic operation theory of all these approaches intended to reduce the switching cycles under light-load or no-load condition either by skipping some switching pulses or reduce the switching frequency. over load protection (olp) to protect the circuit from the damage during over load condition or short condition, a smart olp function is implemented in the LD7575. figure 17 shows the waveforms of the olp operation. under such fault condition, the feedback system will force the voltage loop toward the saturation and thus pull the voltage on comp pin (vcomp) to high. whenever the vcomp trips the olp threshold 5.0v and keeps longer than 30ms (when switching frequency is 65khz), the protection is activated and then turns off the gate output to stop the switching of power circuit. the 30ms delay time is to prevent the false trigger from the power-on and turn-off transient. a divide-2 counter is implemented to reduce the average power under olp behavior. whenever olp is activated, the output is latched off and the divide-2 counter starts to count the number of uvlo(off). the latch is released if the 2nd uvlo(off) point is c ounted then the output is recovery to switching again. by using such protection me chanism, the average input power can be reduced to very low level so that the component temperature an d stress can be controlled within the safe operating area. vcc uvlo(on) uvlo(off) t t comp olp 5.0v t out 30ms switching switching non-switching olp trip level 2nd uvlo(off) olp counter reset fig. 17 ovp (over voltage protection) on vcc the vgs ratings of the no wadays power mosfets are most with maximum 30v. to prevent the vgs from the fault condition, LD7575 is implemented an ovp function on vcc. whenever the vcc voltage is higher than the ovp threshold voltage, the out put gate drive circuit will be shutdown simultaneous thus to stop the switching of the power mosfet until the next uvlo(on).
LD7575 11 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 the vcc ovp function in LD7575 is an auto-recovery type protection. if the ovp condition, usually caused by the feedback loop opened, is not re leased, the vcc will tripped the ovp level again and re-shutdown the output. the vcc is working as a hiccup mode. figure 18 shows its operation. on the other hand, if the o vp condition is removed, the vcc level will get back to normal level and the output is automatically returned to the normal operation. vcc uvlo(on) uvlo(off) t ovp tripped t out switching switching non-switching ovp level fig. 18 fault protection a lot of protection features have been implemented in the LD7575 to prevent the power supply or adapter from being damaged caused by single fault condition on the open or short condition on t he pin of LD7575. under the conditions listed below, the gate output will be off immediately to protect the power circuit --- y rt pin short to ground y rt pin floating y cs pin floating pull-low resistor on the gate pin of mosfet in LD7575, an anti-floating re sistor is implemented on the out pin to prevent the outpu t from any uncertain state which may causes the mosfet working abnormally or false triggered-on. however, such design won?t cover the condition of disconnection of gate resistor rg thus it is still strongly recommended to have a resistor connected on the mosfet gate terminal (as shown in figure 19) to provide extra protection for fault condition. this external pull-low resistor is to prevent the mosfet from damage during power-on under the gate resistor is disconnected. in such single-fault condition, as show in figure 21, the resistor r8 can provide a discharge path to avoid the mosfet from being false-triggered by the current through the gate-to-drain capacitor cgd. therefore, the mosfet is alwa ys pull-low and kept in the off-state whenever the gate re sistor is disconnected or opened in any case. fig. 19
LD7575 12 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 dt dv cgd i bulk ? = fig. 20 protection resistor on the hi-v path in some other hi-v process and design, there may cause a parasitic scr between hv pin, vcc and gnd. as shown in figure 22, a small negative spike on the hv pin may trigger this parasitic scr and causes the latchup between vcc and gnd. and such latchup is easy to damage the chip because of the equivalent short-circuit which is induced by such latchup behavior. as to leadtrend?s proprietary hi-v technology, there is no such parasitic scr in LD7575. figure 23 shows the equivalent circuit of LD7575?s hi-v structure. so that LD7575 is with higher capability to sustain negative voltage than similar products. however, a 40k resistor is recommended to implement on the hi-v path to be played the role as a current limit resistor whenever a negative voltage is applied in any case. fig. 21 fig. 22
LD7575 13 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 reference application circu it --- 10w (5v/2a) adapter pin < 0.15w when pout = 0w & vin = 264vac schematic photocoupler ic1 r7 q1 rs2 ic2 cy1 c5 rt LD7575 rt vcc gnd comp cs out ac input f1 ntc1 cx1 r1a r1b d1a~d1d c1 r6 d4 r4a c4 t1 cr51 c51 r51a l51 c52 r51b c54 fl1 r4b zd51 r56a r56b r54 r52 c55 r55 r53 ic5 z1 4 2 1 3 8 5 d2 c2 6 hv rs1 n l r8 r9
LD7575 14 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 bom p/n component value original r1a n/a r1b n/a r4a 39k , 1206 r4b 39k , 1206 r6 2.2 , 1206 r7 10 , 1206 r8 10k , 1206 r9 10k , 1206 rs1 2.7 , 1206, 1% rs2 2.7 , 1206, 1% rt 100k , 0805, 1% r51a 100 , 1206 r51b 100 , 1206 r52 2.49k , 0805, 1% r53 2.49k , 0805, 1% r54 100 , 0805 r55 1k , 0805 r56a 2.7k , 1206 r56b n/a ntc1 5 , 3a 08sp005 fl1 20mh uu9.8 t1 ei-22 l51 2.7 h p/n component value note c1 22 f, 400v l-tec c2 22 f, 50v l-tec c4 1000pf, 1000v, 1206 holystone c5 0.01 f, 16v, 0805 c51 1000pf, 50v, 0805 c52 1000 f, 10v l-tec c54 470 f, 10v l-tec c55 0.022 f, 16v, 0805 cx1 0.1 f x-cap cy1 2200pf y-cap d1a 1n4007 d1b 1n4007 d1c 1n4007 d1d 1n4007 d2 ps102r d4 1n4007 q1 2n60b 600v, 2a cr51 sb540 zd51 6v2c ic1 LD7575ps sop-8 ic2 el817b ic51 tl431 1% f1 250v, 1a z1 n/a package information
LD7575 15 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 sop-8 dimensions in millimeters dimensions in inch symbols min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.178 0.229 0.007 0.009 i 0.102 0.254 0.004 0.010 j 5.791 6.198 0.228 0.244 m 0.406 1.270 0.016 0.050 0 8 0 8 package information dip-8
LD7575 16 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 dimension in millimeters dimensions in inches symbol min max min max a 9.017 10.160 0.355 0.400 b 6.096 7.112 0.240 0.280 c --- 5.334 --- 0.210 d 0.356 0.584 0.014 0.023 e 1.143 1.778 0.045 0.070 f 2.337 2.743 0.092 0.108 i 2.921 3.556 0.115 0.140 j 7.366 8.255 0.290 0.325 l 0.381 --- 0.015 --- important notice leadtrend technology corp. reserves the right to make changes or corrections to its products at any time without notice. custom ers should verify the datasheets are current and complete before placing order. 0
LD7575 17 leadtrend technology corporation www.leadtrend.com.tw LD7575-ds-04b november 2009 revision history rev. date change notice 00 07/21/?05 original specification. 01 07/28/?05 1. page 2, remove t he unexpected code ?skype.lnk? before the ?ordering information?. 2. page 4, recommended operating condition, change the ?min. supply voltage vcc? from 10v to 11v since the uvlo range is from 9v to 11v. 3. page 9, add the gate resistor on figure 15 and figure 16 to avoid misunderstanding. 4. page 11, add the description ?figure 17 sh ows its operation.? in the section of ?ovp on vcc?. 5. page 13, add ?vin=264vac? on the title. 02 10/24/?05 1. add dip-8 package a. page 1 --- modify the general description ?the LD7575 is offered in both sop-8 and dip-8 package.?. b. page 2 --- add dip-8 data on the ?p in configuration? and ?ordering information?. c. page 4 --- add dip-8 data on the ?absolute maximum rating?. d. page 15 --- add dip-8 package drawing 2. add information of hv current limit resistor and gate-to-gnd resistor a. page 1, 8 (figure13), 9 (figure15,16), 12, 13 --- update the drawing, bom and schematics for such resistors. b. page 11, 12 --- add the sections ?pu ll-low resistor on the gate pin of mosfet?, ?protection resistor on the hi-v path? and figure 19~22. c. page 4 --- add negative voltage limitati on of hv pin on the ?absolute maximum rating?. 3. correction on the block diagram a. page 3 --- add flip-flop on the ovp l oop to be matched with the ovp operation and add the anti-floating resistor on the output. 4. correction on the description of over load protection (olp) a. page 10 --- original descriptio n ?whenever?.30ms (when switching frequency is 100khz)?. where the ?100k hz? should be corrected to ?65khz?. 03 11/28/?05 1. page3, correction on the block diagram by modifying the and gate (following the pwm comparator) to or gate. 2. page 5, correction on the parameters on ?gate drive output? because LD7575 can support to 500ma driving capability but the parameters in the previous datasheet are for 300ma driving current. the output high level will be updated from min. 8v to min. 9v. the rising time will be updated from max. 200ns to max. 160ns. the falling time will be updated from max. 100ns to max. 60ns. all these parameters are for correction and no design change on the related circuits. 04 1/22/?07 revision: block diagram 04a 6/16/08 1. application information/ protecti on resistor on the hi-v path/ ??a 40k resistor is recommended to implement on?.. 2. additional option for green package 04b 6/30 protection resistor on the hi-v path: ?..a 40k resistor is recommended?. continued?

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